1. Technical Field
The present invention relates generally to staged circuits and, more specifically, to staged circuits, which use multi-clocks for timing.
2. Description of Related Art
It has been well known in the art to process data signal inputs in a first stage of a multi-stage circuit and then use the output from the first stage as an input for a subsequent stage. While dynamic circuit applications are known wherein each stage is clocked using a single clock, multi-clock systems are well known. In a typical multi-clock system, a first stage receives first inputs for processing, which are clocked using a first clock. The output of the first stage is fed to the input of a second stage, which is processed using a second clock.
Generally, for the second or later stages of such a design to work, the reset of the previous stage driven by its clock must be slow enough, so that the previous stage outputs are held as the inputs on a subsequent stage long enough for the circuit to properly evaluate.
FIG. 1 is a schematic of a multi-stage circuit having first and second stages being controlled by first and second clocks. In the depicted figure, two stage circuit 100 includes four P-FETs (P-channel Field Effect Transistors), transistors P102, P104, P106, and P108, as well as three N-FETs (N-channel Field Effect transistors), N102, N104, and N106. Each stage contains a logic device, one of devices L102 and L104, and a pair of inverters, I102 and I104 or I106 and I108. Stage 1 comprises logic device L102 being connected to drains of transistors P102 and N102, respectively, where clock C1 is fed to the transistors"" gates. The drain of transistor P102 is connected to an output port of logic device L102. The drain of transistor P102 is further connected to the inputs of inverters I102 and I104 and the drain of transistor P104. The output of inverter I102 feeds to the gate of transistor P104 whose drain is tied to the inputs of inverters I102 and I104.
The output of inverter I104 provides input signal O1 for the stage 2, including logic device L104. The remainder of stage 2 is similar to that of stage 1, comprising logic device L104 being connected to drains of transistors P106 and N104, respectively, where clock C2 is fed to the transistors"" gates. The drain of transistor P106 being connected to an output port of logic device L104 and is further connected to the inputs of inverters I106 and I108. The output of inverter I106 feeds the gates of transistors P108 and N106 whose drains are tied to the inputs of inverters I106 and I108 and to the output port of logic device 104. The evaluation results from logic device 104 are inverted by inverter I108, and then output from stage 2.
Dual clock circuit 100 depicted in FIG. 1 is for use in applications in which the two clocks (C1 and C2) are not underlapped. The design shown in FIG. 1 assumes that the clocks are not underlapped. In other words, C1 rises at the same time C2 falls and more importantly for the second stage, C2 rises and the same time that C1 falls. In the case where this relationship cannot be guaranteed (but the clocks are guaranteed to be underlapped), extra logic must be added so that the outputs of the C1 stage are stable for the inputs of the C2 stage. This extra logic poses performance and stability problems for the system.
It would be advantageous to deal with the underlap condition without adding extra logic to the system.
The present invention relates to a means for solving the undeterminable clock underlap problem associated with multi-stage, multi-clock circuits. The first stage of the multi-stage circuit utilizes a first clock for outputting a signal to the second stage. However, rather than relying on the first clock for triggering both the rising edge and the falling edge of the output, the first stage utilizes a second clock for triggering the falling edge of the output. The second clock also controls the second stage output. In a preferred embodiment of the present invention, this occurs because the first clock stage will not reset until both the first clock is low and second clock are high due to the addition of the second clock signal. The duration of the control clock signal used for controlling the first stage output is increased from an interval defined by the duration of the first clock to an interval defined by the duration of the first clock combined with the inverted second clock signal. The clock falling edge, which triggers the falling edge of the output now becomes the inverted rising edge of the second clock. In accordance with a preferred embodiment, this is accomplished by adding a transistor and inverter to the first stage. The drain of a P-type FET is connected to the source of the P-FET being controlled by the first clock through its gate. The additional P-FET is controlled by an inverted second clock signal, the clock signal being inverted by an inverter connected to the gate of the additional P-FET.
Stability is provided to the first stage by creating a full keeper, which holds the evaluation results from the logic device in the first stage. A pair of transistors are connected by their drains to the evaluation results output of the logic device. The transistors are controlled by an inverter, which is connected to the pair""s bases, wherein the inverter receives the evaluation results. The transistor pair comprises one N-FET and P-FET.